In today's electronic systems, like for example in a computer system, especially the memory system and the linking structures, i.e. the data buses, over which the electronic devices communicate with the additional devices, like for example with memory devices, are of great importance as they determine the capacity of overall electronic systems to a high extent. An important performance feature of data buses hereby is the transmission rate with which the data signals are transmitted over the data buses between the communicating electronic devices. Here, the maximum transmission rate results from the bus clock frequency, the number of bus clocks per data transfer and the number of bytes transmitted per transfer corresponding to the bus width. An increase of performance of the data transmission via a data bus is therefore generally achieved by increasing the bus clock frequency or by an increase of the bus width.
Thus, for example with DRAMs (Dynamic Random Access Memory) the bus clock frequency for the data bus has been increased from about 20 MHz to 400 MHz during the last seven years (up to 2001). This is why it will be increasingly important with faster and more complex electronic systems in the future that the individual system components and devices are capable of communicating safely and reliably with each other with ever higher frequencies and over increasingly wider data buses.
In order to explain the problems of data communication over a parallel data bus reference is made to FIG. 1a now, wherein different bit and/or data signals S1–S3 which are transmitted between two electronic devices via a parallel data bus are illustrated over a period of three clock cycles. As it is illustrated in FIG. 1a in the first clock cycle only one of the data signals, i.e. the signal S1, changes its state from a logical value “0” to a logical value “1”, whereas in the third clock cycle all three data signals S1–S3 simultaneously change from the logical value “0” to the logical signal value “1”.
If a majority of the signal values simultaneously changes from one data word to the next it may be observed in a data transmission over a data bus in practice that different delays in the rise time of the individual signal edges of the data signals occur on the individual bus lines of the data bus. The reason for these different delays and/or signal changes in the signal form is mainly that like in the last case illustrated in FIG. 1 numerous signal values (here all signal values) are simultaneously switched into the same direction, so that particularly much current needs to be made available by the electronic devices for supplying the associated output driver for the individual bus lines of the data buses. This, however, leads to voltage drops of the supply voltage in the electronic device due to unavoidable parasitic effects, like for example line path resistances and inductivities, due to which the output signal of the same and therefore the data signal of the sending electronic device to be transmitted may be largely affected.
FIG. 1b now shows an illustration that theoretically results when numerous single clock signal values of a plurality of signals are illustrated superimposed on each other over a plurality of clock cycles that are operated using random data. From this “superimposition” illustrated in FIG. 1b a so called “data eye” results. This resulting data eye is now an indicator for the signal quality in data transmission, i.e. the resulting data eye indicates in which period of time referring to the clock cycle all signal values transmitted over the data bus are stable, i.e. in which period of time an electronic device receiving the data is able to evaluate the input signals at its inputs, as otherwise a false signal value might be read out and/or interpreted. Thus, the resulting data eye should “ideally” be a rectangle, i.e. represent the ideal rectangled form of the data signals to be transmitted.
In the “real” example illustrated in FIG. 1a and 1b a clock cycle comprises 5 ns, wherein however the resulting data eye may be reduced to an effective width of for example a width of about 2 ns which is finally available for a data interpretation of the transmitted signal data due to the above described interfering effect.
This represents an increasing problem especially for complex electronic systems expected in the future, as with higher clock frequencies and with greater bus widths the resulting data eye may disappear completely, so that no reliable signal transmission between two electronic devices over the data bus is possibly anymore. This finally leads to the fact that a desired and necessary increase of the clock cycle and the bit width of the data signals can not be realised anymore for future electronic systems due to the mentioned problems and therefore the system limits of electronic systems will soon be reached.
Apart from that it has to be noted that the resulting data eye in an electronic system is further reduced by effects like signal line couplings, design asymmetries on the transmitter and receiver side, etc. Therefore, these effects in the electronic system further contribute to an impairment of the data transmission.
As it was illustrated above, the basic component which leads to a decrease of the effective width of the resulting data eye in a data transmission is mainly the simultaneous switching of identical signal values which leads to internal supply voltage drops in the electronic devices communicating with each other. This effect is called synchronous switching noise “SSN” in the following.
Up to now the synchronous switching noise SSN was only fought by general switching measures by providing voltage supplies, which are independent from each other and as good as possible, of the individual output signal drivers of the electronic devices on an electronic semiconductor device. However, these methods meanwhile reach their technical limits and can momentarily not be improved anymore and/or only with very high costs.